This application relies for priority upon Korean Patent Application No. 2000-076375, filed on Dec. 14, 2000, the contents of which are herein incorporated by reference in their entirety.
The present invention generally relates to semiconductor memory devices, and more specifically to a non-volatile semiconductor memory device capable of preventing program disturb due to a noise voltage induced at a string select line and a program method thereof.
Demand for semiconductor memory devices capable of electrically erasable and programmable without a refresh function to retain data stored therein is on the rise. Further, attempts for improving the storage capacitance and integration of the memory device are increasing. A non-volatile memory device offers the large-scaled storage capacitance and high integration, without refresh of such a stored data, and one example of the device is a NAND-type flash memory device. Since the NAND-type flash memory device retains the data even in a case of power-off, it is widely used in applications where the possibility of power supply interruption is present such as a portable terminal equipment, a portable computer, and etc.
Conventional non-volatile semiconductor memory devices like the NAND-type flash memory device include a type of electrically erasable and programmable read-only memory (EEPROM) device typically referred to as xe2x80x9ca flash EEPROM devicexe2x80x9d. Flash EEPROM devices generally include a semiconductor substrate (or bulk) of a first conductivity type, e.g. P-type; spaced source and drain regions of a second conductivity type, e.g. N-type, in the substrate; a channel region at a face of the substrate, between the spaced source and drain regions; a floating gate for storing charge carriers when the device is programmed; and a control gate which overlies the floating gate, opposite the channel region.
An array in the well-known NAND-type flash memory device is shown in FIG. 1. Referring to FIG. 1, the memory cell array includes a plurality of cell strings 10 corresponding to bit lines. Here, two bit lines BL0 and BL1 and two cell strings 10 corresponding thereto are exemplified in FIG. 1, for the sake of convenience. Each of the cell strings 10 is composed of a string select transistor SST as a first select transistor, a ground select transistor GST as a second select transistor, and a plurality of EEPROM cells MC0 through MC15 being serially connected between the select transistors SST and GST. The string select transistor SST has a drain connected to a corresponding bit line and a gate connected to string select line SSL. The ground select transistor GST has a source connected to a common source line CSL and a gate connected to a ground select line GSL. Between the source of the string select transistor SST and the drain of the ground select transistor GST, the flash EEPROM cells MC15xcx9cMC0 are serially connected, which are respectively connected to word lines WL15xcx9cWL0 corresponding thereto.
Initially, the flash EEPROM cells in the memory cell array are erased to a certain threshold voltage, e.g. xe2x88x923V. For the purpose of programming the flash EEPROM cells, a high voltage, e.g. 20V, is applied to a word line of a select memory cell for a predetermined time. Thus, the select memory cell is charged to a higher threshold voltage while the threshold voltages of unselect EEPROM cells remain unchanged.
A problem arises when it is desired to program a selected flash EEPROM cell along a word line without programming unselect memory cells on the same word line. When a program voltage is applied to the word line, the voltage is applied not only to the selected flash EEPROM cell but also to the unselected flash EEPROM cells along the same word line for programming. Thus, the unselected flash EEPROM cell, in particular the flash EEPROM cell adjacent to the selected cell, is programmed. The unintentional programming of an unselected cell connected to a selected word line is referred to herein as xe2x80x9cprogram disturb.xe2x80x9d
One of the ways for preventing program disturb is a program inhibit method employing a self-boosting scheme. The program inhibit method employing the self-boosting scheme is disclosed in U.S. Pat. No. 5,677,873 entitled xe2x80x9cMethod of Programming Flash EEPROM Integrated Circuit Memory Devices to Prevent Inadvertent Programming of Nondesignated NAND memory cells thereinxe2x80x9d, and U.S. Pat. No. 5,991,202 entitled xe2x80x9cMethod for Reducing Program Disturb during Self-Boosting in a NAND flash Memoryxe2x80x9d, which are incorporated herein by reference.
FIG. 2 is a timing diagram showing a programming operation according to the program inhibit method employing the self-boosting scheme. A ground path is blocked by applying 0V to the gate of the ground select transistor GST. A zero voltage (0V) potential is applied to a selected bit line, e.g., BL0, and a power supply voltage Vcc as the program inhibit voltage such as 3.3 V or 5V is applied to an unselected bit line, e.g., BL1. At the same time, the power supply voltage Vcc is applied to the gate of the string select transistor SST connected to the bit line BL1, which causes the source of the string select transistor SST (or the channel of a program inhibited cell transistor) to be charged up to Vcc-Vth (Vth is a threshold voltage of the string select transistor). Here, the string select transistor SST is substantially blocked or shut off. A time period for the aforementioned operation is referred to xe2x80x9ca bit line setup periodxe2x80x9d.
Next, the channel voltage Vchannel of the program inhibited cell transistor is boosted by applying a high voltage, e.g. a program voltage Vpgm, to the selected word line, and applying a lower, e.g. a pass voltage Vpass, to the unselected word lines. Thus, Fowler-Nordheim (F-N) tunneling is prevented between a floating gate and the channel region. This retains the initial erased state of the program inhibited cell transistor. A time period for such an operation is referred to xe2x80x9ca program periodxe2x80x9d. After programming for the select memory cell is complete, a recovery operation for discharging charges of the bit line is performed.
The program inhibit method employing the self-boosting scheme has a problem when applied to the flash memory device. Typically, the interval between adjacent signal lines decreases in accordance with the increasing integration of the device, so that coupling between the lines readily occurs due to parasitic capacitance between adjacent signal lines. To program a memory cell, e.g. MC15, adjacent the string select transistor SST, when the program voltage Vpgm is applied to a select word line WL15 connected to the memory cell MC 15, a nominal voltage of the string select line SSL is boosted higher than the power supply voltage Vcc due to the coupling with the select word line WL15. This is shown in FIG. 2. The voltage rise of the string select line SSL causes the charges produced by the self-boosting operation in the channel of the program inhibit cell transistor to go out to the unselected bit line. In other words, as shown in FIG. 2, the channel voltage Vchannel of the program inhibited cell transistor (or an inhibit voltage Vinhibit) is lowered by xcex94V in proportion to the voltage rise of the string select line SSL. Thus, a program disturb where the program inhibited cell transistor is programmed undesirably occurs.
It is, therefore, an object of the present invention to provide a non-volatile semiconductor memory device capable of preventing program disturb that might otherwise occur while programming a memory cell adjacent to a string select line, and a program method thereof.
In order to attain the above objects, according to an aspect of the present invention, there is provided a method of programming in a non-volatile semiconductor memory device. The memory device includes a memory cell array formed of a plurality of cell strings each of which is connected through a first and second select transistors between a bit line and a common source line and has a plurality of memory cell transistors, formed in a pocket P-well, having control gates of the memory cell transistor being respectively coupled to word line arranged in parallel between a first and second select lines. For the purpose of programming in the non-volatile semiconductor memory device, in a state that the first select line is biased to a first voltage, one of the first voltage and a second voltage is respectively applied to the bit lines corresponding to cell strings in accordance with data bits to be programmed. Here, the second voltage is lower than the first voltage. Next, the first select line is biased to a third voltage between the first and second voltages. Afterwards, program voltage is applied to a select word line of the word lines.
The first voltage is a power supply voltage, and the second voltage is a ground voltage. The third voltage is enough to turn off the first select transistor connected to the bit line corresponding to the data being programmed.
The third voltage is enough to turn off the first select transistor connected to the bit line corresponding to the data bit being programmed.
The third voltage is between a fourth and fifth voltage. The fourth voltage is enough to turn on the first select transistor connected to the bit line corresponding to the data bit being programmed, and the fifth voltage is a shut-off voltage on the basis of the bit line corresponding to the data bit being program inhibited. The shut-off voltage is given by the first voltagexe2x80x94(xcex2xc3x97Vpgm); where xcex2 is a coupling ratio of word line to string select line, and Vpgm is the program voltage.
According to another aspect of this invention, there is provided a non-volatile semiconductor memory device having a memory cell array as one memory block. The memory cell array is formed of a string select transistor whose drain is connected to a bit line corresponding thereto, a ground select transistor whose source is connected to a common source line, a plurality of cell strings having a plurality of memory cell transistors serially connected between a source of the string select transistor and a drain of the ground select transistor, word lines respectively connected to control gates of the memory cell transistors, string select line commonly connected to gates of the string select transistors, and a ground select line commonly connected to gates of the ground select transistors. The non-volatile semiconductor memory device further includes control means and a page buffer circuit. The control means separately controls potentials of the select lines and word lines according to a bit line setup period, a string select line setup period, a program period, and a discharge period of the program cycle. The page buffer circuit respectively applies one of the first and second voltages to the bit lines in accordance with data bits to be programmed in the memory cell array, during the bit line setup period of the program cycle. The control means biases the string select line to the first voltage during the bit line setup period, and to a third voltage between the first and second voltages during the string select line setup and program periods.
As is apparent from the foregoing, according to the device and method of the invention, program disturb due to a noise voltage induced at the string select line can be prevented, when the program voltage is applied to a word line adjacent to the string select line.
The foregoing features and advantages of the invention will be more fully described in the accompanying drawings.